ResponsibilitiesWorkcloselywiththedesignteamtoreviewandunderstandspecifications/architectures/micro-architecturesDefinetestplansDevelopblocklevelandchiplevelverificationenvironmentsProducefunctional/codecoveragemetricsRunregressionanddebug/triagefailuresinsimulationenvironmentValidatefeaturesandworkwithsoftwareteamstodebugissuesinthelabQualificationsRequired:BSEEwith7+yearsorMSEEwith5+yearsexperiencesAdvancedknowledgeofstandardASIC/FPGAverificationflowsincludingsimulation,testbenchdevelopment,andpostsiliconvalidationExcellentknowledgeofSystemVerilogandVerilogExperienceindevelopingtestbenchesusingtheOVM,VMMorUVMmethodologyGoodknowledgewithC/C++ExperiencewitheitherPerlorPythonscriptsKnowledgeofindustryhighspeedinterfacestandardprotocols(PCIExpress,DDR,NANDFlashetc.)stronglydesiredExperienceincomputerstorageandnetworkingisdesiredShouldbeateamplayerwithexcellentcommunicationskillsandthedesiretotakeondiversechallenges
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康惠（惠州）半导体有限公司
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